?2001 fairchild semiconductor corporation huf76639s3s rev. c0 huf76639s3s n-channel logic level ultrafet power mosfet 100 v, 50 a, 27 m? packaging symbol features ? ultra low on-resistance -r ds(on) = 0.026 ?, v gs = 10v -r ds(on) = 0.027 ?, v gs = 5v simulation models - temperature compensated pspice? and saber? electrical models - spice and saber thermal impedance models - www.fairchildsemi.com peak current vs pulse width curve uis rating curve switching time vs r gs curves ordering information absolute maximum ratings t c = 25 o c, unless otherwise specified product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html for severe environm ents, see our automotive hufa series. all fairchild semiconductor products are manufactured, assembled and tested under iso9000 and qs9000 quality systems certif ication. jedec to-263ab gate s ource drain (flange) d g s part number package brand to-263a b 76639s HUF76639S3ST units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss 100 v drain to gate voltage (r gs = 20k ? ) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 100 v gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 16 v drain current continuous (t c = 25 o c, v gs = 5v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d continuous (t c = 25 o c, v gs = 10v) (figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d continuous (t c = 100 o c, v gs = 5v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d continuous (t c = 100 o c, v gs = 4.5v) (figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d pulsed drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm 50 51 35 34 figure 4 a a a a pulsed avalanche rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . uis fi gures 6, 17, 18 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d derate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 1.2 w w/ o c operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 175 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t l package body for 10s, see techbrief tb334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c notes: 1. t j = 25 o c to 150 o c. caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress only ratin g and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. data sheet october 2013 HUF76639S3ST
?2001 fairchild semiconductor corporation huf76639s3s rev. c0 electrical specifications t c = 25 o c, unless otherwise specified parameter symbol test conditions min typ max units off state specifications drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v (figure 12) 100 - - v i d = 250 a, v gs = 0v , t c = -40 o c (figure 12) 90 - - v zero gate voltage drain current i dss v ds = 95v, v gs = 0v - - 1 a v ds = 90v, v gs = 0v, t c = 150 o c - - 250 a gate to source leakage current i gss v gs = 16v - - 100 na on state specifications gate to source threshold voltage v gs(th) v gs = v ds , i d = 250 a (figure 11) 1 - 3 v drain to source on resistance r ds(on) i d = 51a, v gs = 10v (figures 9, 10) - 0.023 0.026 ? i d = 35a, v gs = 5v (figure 9) - 0.024 0.027 ? i d = 34a, v gs = 4.5v (figure 9) - 0.025 0.028 ? thermal specifications thermal resistance junction to case r jc to-263 - - 0.83 o c/w thermal resistance junction to ambient r ja --62 o c/w switching specifications (v gs = 4.5v) turn-on time t on v dd = 50v, i d = 34a v gs = 4.5v, r gs = 12 ? (figures 15, 21, 22) - - 336 ns turn-on delay time t d(on) -17-ns rise time t r - 207 - ns turn-off delay time t d(off) -83-ns fall time t f - 136 - ns turn-off time t off - - 328 ns switching specifications (v gs = 10v) turn-on time t on v dd = 50v, i d = 51a v gs = 10v, r gs = 12 ? (figures 16, 21, 22) - - 96 ns turn-on delay time t d(on) -10-ns rise time t r -55-ns turn-off delay time t d(off) - 151 - ns fall time t f - 110 - ns turn-off time t off - - 392 ns gate charge specifications total gate charge q g(tot) v gs = 0v to 10v v dd = 50v, i d = 35a, i g(ref) = 1.0ma (figures 14, 19, 20) -7186nc gate charge at 5v q g(5) v gs = 0v to 5v - 39 47 nc threshold gate charge q g(th) v gs = 0v to 1v - 2.0 2.4 nc gate to source gate charge q gs -6-nc gate to drain ?miller? charge q gd -19-nc capacitance specifications input capacitance c iss v ds = 25v, v gs = 0v, f = 1mhz (figure 13) - 2400 - pf output capacitance c oss - 520 - pf reverse transfer capacitance c rss - 140 - pf source to drain diode specifications parameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 35a - - 1.25 v i sd = 15a - - 1.0 v reverse recovery time t rr i sd = 35a, di sd /dt = 100a/ s - - 137 ns reverse recovered charge q rr i sd = 35a, di sd /dt = 100a/ s - - 503 nc huf76639s3s
?2001 fairchild semiconductor corporation huf76639s3s rev. c0 typical performance curves figure 1. normalized power dissipation vs case temperature figure 2. maximum cont inuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance figure 4. peak current capab ility t c , case temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 17 5 0.2 0.4 0.6 0.8 1.0 1.2 125 150 10 20 30 40 50 60 25 50 75 100 125 150 17 5 0 i d , drain current (a) t c , case temperature ( o c) v gs = 10v v gs = 4.5v 0.1 1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 0.01 2 t, rectangular pulse duration (s) z jc , normalized single pulse notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c p dm t 1 t 2 duty cycle - descending order 0.5 0.2 0.1 0.05 0.01 0.02 thermal impedance 100 1000 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 -5 50 i dm , peak current (a) t, pulse width (s) transconductance may limit current in this region t c = 25 o c i = i 25 175 - t c 150 for temperatures above 25 o c derate peak current as follows: v gs = 10v v gs = 5v huf76639s3s
?2001 fairchild semiconductor corporation huf76639s3s rev. c0 figure 5. forward bias safe operating area note: refer to fairchild application notes an9321 and an 9322. figure 6. unclamped inductive switching capability figure 7. transfer characteristics fig ure 8. saturation characteristics figure 9. drain to source on resistance vs gate voltage and drain current figure 10. normalized drain to source on resistance vs junction temperature typical performance curves (continued) 10 100 110100 300 1 30 0 100 s 10ms 1ms v ds , drain to source voltage (v) i d , drain current (a) limited by r ds(on) area may be operation in this t j = max rated single pulse t c = 25 o c 0.01 0.1 1 10 10 0 10 100 1 500 i as , avalanche current (a) t av , time in avalanche (ms) t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] starting t j = 25 o c starting t j = 150 o c 25 50 75 100 1.5 2.0 2.5 3.0 3.5 4. 0 0 i d, drain current (a) v gs , gate to source voltage (v) pulse duration = 80 s duty cycle = 0.5% max v dd = 15v t j = 175 o c t j = 25 o c t j = -55 o c 25 50 75 100 01234 5 0 i d , drain current (a) v ds , drain to source voltage (v) v gs = 3v v gs = 3.5v pulse duration = 80 s duty cycle = 0.5% max t c = 25 o c v gs = 5v v gs = 10v v gs = 4v 25 30 35 40 24681 0 20 i d = 15a v gs , gate to source voltage (v) i d = 51a r ds(on) , drain to source on resistance (m ? ) i d = 35a pulse duration = 80 s duty cycle = 0.5% max t c = 25 o c 1.0 1.5 2.0 2.5 3.0 -80 -40 0 40 80 120 160 20 0 0.5 normalized drain to source t j , junction temperature ( o c) on resistance v gs = 10v, i d = 51a pulse duration = 80 s duty cycle = 0.5% max huf76639s3s
?2001 fairchild semiconductor corporation huf76639s3s rev. c0 figure 11. normalized gate threshold voltage vs junction temperature figure 12. normalized drain to source breakdown voltage vs junction temperature figure 13. capacitance vs drain to source voltage note: refer to fairchild application notes an7254 and an 7260. figure 14. gate charge waveforms for constant gate current figure 15. switching time vs gate resistance fi gure 16. switching time vs gate resistance typical performance curves (continued) 0.6 0.8 1.0 1.2 -80 -40 0 40 80 120 160 200 0.4 normalized gate t j , junction temperature ( o c) v gs = v ds , i d = 250 a threshold voltage 1.0 1.1 1.2 -80 -40 0 40 80 120 160 200 0.9 t j , junction temperature ( o c) normalized drain to source breakdown voltage i d = 250 a 100 1000 0.1 1 10 10 0 5000 40 c, capacitance (pf) v ds , drain to source voltage (v) v gs = 0v, f = 1mhz c iss = c gs + c gd c oss ? c ds + c gd c rss = c gd 2 4 6 8 10 0 153045607 5 0 v gs , gate to source voltage (v) v dd = 50v q g , gate charge (nc) i d = 51a i d = 35a waveforms in descending order: i d = 15a 100 200 300 400 0 1020304050 0 switching time (ns) r gs , gate to source resistance ( ? ) v gs = 4.5v, v dd = 50v, i d = 34a t r t f t d(on) t d(off) 200 300 400 500 600 0 1020304050 0 100 switching time (ns) r gs , gate to source resistance ( ? ) v gs = 10v, v dd = 50v, i d = 51a t d(off) t r t d(on) t f huf76639s3s
?2001 fairchild semiconductor corporation huf76639s3s rev. c0 test circuits and waveforms figure 17. unclamped energy test circuit figure 18. unclamped energy waveforms figure 19. gate charge test circuit figure 20. gate charge waveforms figure 21. switching time test circuit figure 22. switching time waveform t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 1v q g(5) v gs = 5v q g(tot) v gs = 10 v v ds v gs i g(ref) 0 0 q gs q gd v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 huf76639s3s
?2001 fairchild semiconductor corporation huf76639s3s rev. c0 pspice electrical model .subckt huf76639 2 1 3 ; rev 26 july 1999 ca 12 8 4.2e-9 cb 15 14 4.2e-9 cin 6 8 2.27e-9 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 118.2 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1.0e-9 lgate 1 9 5.1e-9 lsource 3 7 3.1e-9 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 15.8e-3 rgate 9 20 1.94 rldrain 2 5 10 rlgate 1 9 51 rlsource 3 7 31 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 3.6e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value = {(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*99),3.5))} .model dbodymod d (is = 2.6e-12 rs = 2.65e-3 ikf = 6 trs1 = 1.5e-3 trs2 = 3.5e-6 cjo = 2.1e-9 tt = 5.6e-8 m = 0.52) .model dbreakmod d (rs = 2.5e-1 trs1 = 1e-4 trs2 = -1e-6) .model dplcapmod d (cjo = 2.6e-9 is = 1e-30 m = 0.89 n = 10) .model mmedmod nmos (vto = 1.77 kp = 7 is = 1e -30 n = 10 tox = 1 l = 1u w = 1u rg = 1.94) .model mstromod nmos (vto = 2.06 kp = 95 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 1.48 kp = 0.12 is = 1e- 30 n = 10 tox = 1 l = 1u w = 1u rg = 19.4 rs = .1) .model rbreakmod res (tc1 = 1.05e-3 tc2 = -5e-7) .model rdrainmod res (tc1 = 8.5e-3 tc2 = 2.3e-5) .model rslcmod res (tc1 = 3.4e-3 tc2 = 2.5e-6) .model rsourcemod res (tc1 = 1e-3 tc2 = 1e-6) .model rvthresmod res (tc1 = -1.9e-3 tc2 = -4.5e-6) .model rvtempmod res (tc1 = -1.7e-3 tc2 = 1.5e-6) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -4.5 voff = -2.0) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -2.0 voff = -4.5) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = -0.5 voff = 0.3) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = 0.3 voff = -0.5) .ends note: for further discussion of the pspice m odel, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1 991, written by william j. hepp and c. frank w heatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 huf76639s3s
?2001 fairchild semiconductor corporation huf76639s3s rev. c0 saber electrical model rev 26 july 1999 template huf76639 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 2.6e-12, cjo = 2.1e-9, tt = 5.6e-8, m = 0.52, n=10) d..model dbreakmod = () d..model dplcapmod = (cjo = 2.6e-9, is = 1e-30, m = 0.89) m..model mmedmod = (type=_n, vto = 1.77, kp = 7, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.06,kp = 95, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.48, kp = 0.12,is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.5, voff = -2.0) sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -2.0, voff = -4.5) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.3) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.3, voff = -0.5) c.ca n12 n8 = 4.2e-9 c.cb n15 n14 = 4.2e-9 c.cin n6 n8 = 2.27e-9 d.dbody n7 n71 = model = dbodymod d.dbreak n72 n11 = model = dbreakmod d.dplcap n10 n5 = model = dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1.0e-9 l.lgate n1 n9 = 5.1e-9 l.lsource n3 n7 = 3.1e-9 m.mmed n16 n6 n8 n8 = model = mmedmod, l = 1u, w = 1u m.mstrong n16 n6 n8 n8 = model = mstrongmod, l = 1u, w = 1u m.mweak n16 n21 n8 n8 = model = mweakmod, l = 1u, w = 1u res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = -5e-7 res.rdbody n71 n5 = 2.65e-3, tc1 = 1.5e-3, tc2 = 3.5e-6 res.rdbreak n72 n5 = 2.5e-1, tc1 = 1e-4, tc2 = -1e-6 res.rdrain n50 n16 = 15.8e-3, tc1 = 8.5e-3, tc2 = 2.3e-5 res.rgate n9 n20 = 1.94 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 51 res.rlsource n3 n7 = 31 res.rslc1 n5 n51 = 1e-6, tc1 = 3.4e-3, tc2 = 2.5e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 3.6e-3, tc1 = 1e-3, tc2 = 1e-6 res.rvtemp n18 n19 = 1, tc1 = -1.7e-3, tc2 = 1.5e-6 res.rvthres n22 n8 = 1, tc1 = -1.9e-3, tc2 = -4.5e-6 spe.ebreak n11 n7 n17 n18 = 118.2 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model = s1amod sw_vcsp.s1b n 13 n12 n13 n8 = model = s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model = s2amod sw_vcsp.s2b n 13 n15 n14 n13 = model = s2bmod v.vbat n22 n19 = dc = 1 equations { i (n51->n50) + = iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/99))** 3.5)) } } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 rdbody rdbreak 72 71 huf76639s3s
?2001 fairchild semiconductor corporation huf76639s3s rev. c0 spice thermal model rev 26 july 1999 huf76639t ctherm1 th 6 3.2e-3 ctherm2 6 5 8.5e-3 ctherm3 5 4 1.2e-2 ctherm4 4 3 1.6e-2 ctherm5 3 2 5.5e-2 ctherm6 2 tl 1.5 rtherm1 th 6 8.0e-3 rtherm2 6 5 6.8e-2 rtherm3 5 4 9.2e-2 rtherm4 4 3 2.0e-1 rtherm5 3 2 2.4e-1 rtherm6 2 tl 5.2e-2 saber thermal model saber thermal model huf76639t template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 3.2e-3 ctherm.ctherm2 6 5 = 8.5e-3 ctherm.ctherm3 5 4 = 1.2e-2 ctherm.ctherm4 4 3 = 1.6e-2 ctherm.ctherm5 3 2 = 5.5e-2 ctherm.ctherm6 2 tl = 1.5 rtherm.rtherm1 th 6 = 8.0e-3 rtherm.rtherm2 6 5 = 6.8e-2 rtherm.rtherm3 5 4 = 9.2e-2 rtherm.rtherm4 4 3 = 2.0e-1 rtherm.rtherm5 3 2 = 2.4e-1 rtherm.rtherm6 2 tl = 5.2e-2 } rtherm4 rtherm6 rtherm5 rtherm3 rtherm2 rtherm1 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 th junction case huf76639s3s
?2001 fairchild semiconductor corporation huf76639s3s rev. c0 huf76639s3s trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. * trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or desi gn. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditio ns, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical components in life support de vices or systems without the express written approval of fai rchild semiconductor corporation. as used here in: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms accupower? 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